1. Field of the Invention
This invention relates to the field of digital testing apparatus for analyzing high speed data.
2. Description of the Prior Art
The objective of digital testing is to determine whether for a given input signal (usually called "input test vector" since it is a set of parallel input bits) the output value (or state) of the device under test (DUT) is in error for any of its output channels. The test must determine the location of the error (i.e., specific bit and state) and the nature of the error (i.e., "1" instead of "0" or vice versa). State-of-the-art commercially available digital testers can test silicon based integrated circuits at speeds of the order of 200 MHz. Digital testing at 1-2 GHz rates as required for LSI GaAs integrated circuits or high-speed superconductive devices, however, is impossible with any known technology. This is because of the lack of a established high-speed technology that is capable of satisfying some rather stringent test requirements which include receiving the DUT's high-speed output data, transferring the data to the tester while avoiding transmission line effects, and converting the high-speed data to low-speed data so that they can be compared with the expected reference data which are stored in a conventional low-speed memory.
A typical 100 MHz clock digital tester provides data pulsewidths of 10 ns with combined rise and fall times of about 30% the pulsewidth or 1.5 ns each. The timing resolution or accuracy with which the edges of the pulses are applied to the inputs of the DUT is typically 3-5% of the pulsewidth or about 300 ps. This requirement arises because of the need to verify the predicted propagation delay through the DUT. Thus the tester must provide input test vectors whose elements (or bits) are positioned in time as accurately as possible. The tester skew (defined as the maximum timing error of a tester that measures the arrival of a pulse simultaneously applied to every pin of the tester's input) is typically 10% of the pulsewidth or 1 ns. By extrapolating these guidelines, the specifications of a 1.5 GHz (RZ) digital tester can be determined. The width of each bit is 666 ps which implies that square waveforms of about 330 ps must be generated having rise and fall times of 50 ps. For 5% time resolution, the tester must be able to place the pulse edges as accurately as 35 ps. The system skew figure must be kept to less than 66 ps.
In a general high-speed testing scenario, a demultiplexer (DMUX) or serial-to-parallel converter is used to slow down the high-speed output DUT data so that they can be tested or stored using conventional low speed electronics. The highest speed DMUX device can operate at 1.5 G bit/s data rates and has a rise and fall time of 150 ps. This rise and fall time speed exceeds the specifications of the 1.5 GHz tester by a factor of 2. Consequently, there is a need for a digital testing device capable of testing high-speed data in excess of 1 GHz.